Successive Approximation ADC Design and Timing

Successive approximation analog-to-digital converters (SAR ADCs) are a cornerstone of modern mixed-signal design, striking an optimal balance between speed, power, and resolution. They achieve this by implementing a highly efficient binary search algorithm in hardware, making them ideal for applications from industrial control to medical instrumentation where moderate sampling rates and medium-to-high resolution are required. Understanding their operation and timing constraints is key to designing robust data acquisition systems.

The Binary Search Algorithm at the Core

At its heart, a successive approximation ADC operates on a principle identical to the classic "guess a number" game. If you are told to guess a number between 0 and 128, the most efficient strategy is to start at the midpoint (64) and ask, "Is it higher or lower?" Based on the answer, you then halve the remaining range and guess again. A binary search algorithm systematically narrows down the possible range of an unknown value with each comparison.

The ADC translates this logic to voltage. For an N-bit converter, the full-scale input voltage range represents all possible numbers from 0 to $2^N-1$. The converter starts by testing the most significant bit (MSB). It asks, "Is the input voltage greater than half of the full-scale voltage (i.e., is the MSB = 1)?" The answer determines the state of the MSB. The converter then moves to the next bit, using the result of the previous comparison to set a new, narrower test voltage, and repeats the process down to the least significant bit (LSB). Crucially, this process requires exactly N comparison steps to resolve an N-bit value, providing a deterministic and predictable conversion time.

Key Components and Operational Phases

A SAR ADC comprises three fundamental building blocks: a comparator, a digital-to-analog converter (DAC), and a successive approximation register (SAR). Their interaction defines the two primary phases of operation: the sampling phase and the conversion (or bit-cycling) phase.

During the sampling phase, the input signal is connected to a sample-and-hold circuit. The aperture time is the critical window during which this circuit captures and holds a stable snapshot of the analog input voltage. Any change in the input during this aperture creates an error, so the sample must be taken quickly relative to the signal's frequency.

Once the voltage $V_{IN}$ is held, the conversion phase begins. The SAR, initialized to all zeros, takes control. For an 8-bit conversion:

1. The SAR sets the DAC's MSB (bit 7) to 1, producing a test voltage $V_{DAC}=V_{REF}/2$.
2. The comparator evaluates: Is $V_{IN}>V_{DAC}$?

• If YES: The MSB remains a '1'. The SAR now knows $V_{IN}$ is in the upper half of the range.
• If NO: The MSB is cleared to '0'. $V_{IN}$ is in the lower half.

1. The SAR moves to bit 6. It sets this bit to 1, which commands the DAC to output a voltage at the midpoint of the new search range (e.g., $V_{REF}/4$ if MSB=0, or $3V_{REF}/4$ if MSB=1).
2. The comparator makes the decision for bit 6, and the process repeats for bits 5 down to 0.

The successive approximation register is the logic engine that sequences this process, updating the DAC code based on each comparator decision. After N clock cycles, the final digital code stored in the SAR is the converted output.

Determining Conversion Speed and Timing Constraints

The maximum speed of a SAR ADC is not defined by a single number but by a chain of timing constraints. The total conversion time, $T_{CONV}$, is the sum of the sampling time and the bit-cycling time: $T_{CONV}=T_{ACQ}+N\times T_{CYC}$.

• Sample Rate vs. Conversion Time: The sample rate is simply the inverse of the total conversion time ($f_s=1/T_{CONV}$). To increase sample rate, you must minimize $T_{CONV}$.
• Aperture Time & Acquisition Time ($T_{ACQ}$): This is the time needed for the internal sample-and-hold capacitor to charge to the input voltage level within the required accuracy. It is driven by the circuit's RC time constant and the settling time of any input buffer amplifiers. Inadequate acquisition time results in a static offset error.
• DAC Settling Time: This is the most critical factor during the bit-cycling phase. Each time the SAR changes the input code to the internal DAC, its output must settle to within a fraction of an LSB before the comparator can make a valid decision. This settling time ($T_{SETTLE}$) dictates the minimum usable clock period, $T_{CYC}$. If the DAC output hasn't settled, the comparator makes a decision based on an incorrect voltage, corrupting that bit and all subsequent bits.

Therefore, the maximum conversion speed is ultimately limited by the slower of two factors: how fast you can acquire a clean sample, and how fast your DAC can settle to the necessary precision during each binary search step.

Common Pitfalls

Underestimating DAC Settling Time Requirements. Using a clock frequency that is too high for the internal DAC is a primary design error. If $T_{CYC}<T_{SETTLE}$, the converter will produce inaccurate results, often characterized by missing codes or non-monotonic behavior. Always consult the ADC's datasheet for the maximum specified clock frequency and ensure your system clock meets this constraint with margin.

Ignoring Input Signal Dynamics During Aperture. The aperture time defines a small but finite window. If the input signal changes significantly during this window, the sampled voltage is ambiguous, leading to aperture jitter. This effect becomes a major source of error for high-frequency input signals, increasing noise and distorting the digitized waveform. The solution is to ensure the sample-and-hold circuit has a sufficiently short aperture time for your application's maximum input frequency.

Neglecting Comparator Noise and Metastability. The comparator is not a perfect decision-maker. Noise on its input can cause an incorrect decision, especially when $V_{IN}$ is very close to $V_{DAC}$. Furthermore, if the comparator is forced to make a decision before its internal nodes have fully resolved (a condition called metastability), it can output an invalid logic level, causing the SAR logic to fail. Adequate cycle time ($T_{CYC}$) must be allocated not just for DAC settling, but also for comparator resolution.

Summary

• SAR ADCs implement a hardware binary search algorithm, determining each bit from MSB to LSB, which requires exactly N comparisons for N-bit resolution.
• The three essential components are a comparator for decisions, a DAC to generate test voltages, and a successive approximation register (SAR) to control the sequence.
• Maximum conversion speed is determined by the sum of the input acquisition time and N times the bit-cycling period, where the cycle period is dominated by DAC settling time.
• The sample rate is the inverse of the total conversion time, and achieving a higher rate requires optimizing both the sampling circuitry and the internal DAC's settling performance.
• Careful timing analysis is required to avoid errors from inadequate DAC settling, input signal change during the aperture time, and comparator noise or metastability.