DL: Verilog Fundamentals for Digital Design

Verilog is the cornerstone language for modern digital design, enabling engineers to describe, simulate, and synthesize complex integrated circuits and FPGAs efficiently. Unlike traditional software programming, you are describing physical hardware structures and their concurrent behavior, making it a critical skill for anyone in computer engineering, embedded systems, or ASIC design. Mastering Verilog fundamentals allows you to translate abstract logic diagrams and state machines into precise, implementable designs that can be turned into real silicon.

The Building Block: Modules and Ports

Every Verilog design is constructed from modules, which are the fundamental building blocks analogous to chips or components on a circuit board. A module defines a design's interface through its ports and encapsulates its internal functionality. Ports are declared as input, output, or inout (bidirectional), specifying how the module communicates with the outside world.

Consider a simple 2-input AND gate. You describe it not by drawing transistors, but by declaring a module:

module and_gate (
    input  wire a,
    input  wire b,
    output wire y
);
    assign y = a & b;
endmodule

The keyword wire represents a physical electrical net that connects points within the design. This example uses a continuous assignment (assign) to describe a pure combinational logic function. The real power of Verilog emerges when you instantiate modules within other modules, creating a hierarchical design that mirrors the physical hierarchy of a circuit board.

Describing Logic: Dataflow and Behavioral Styles

The behavioral style uses always blocks to describe more complex, procedural behavior. An always block contains statements that execute sequentially, but the block itself runs concurrently with other assignments and always blocks in the design. Crucially, you must specify a sensitivity list that tells the simulator when the block should be triggered. For combinational logic, you use the wildcard always @(*), which triggers the block whenever any signal on the right-hand side of its assignments changes. Inside such a block, you use = (blocking) assignments for simple combinational descriptions.

always @(*) begin
    if (sel == 2'b00) y = a;
    else if (sel == 2'b01) y = b;
    else y = c;
end

This block describes a multiplexer. The key is that for synthesis, the always @(*) block must define y for every possible input condition to avoid inferring unintended latches.

Implementing Sequential Logic with Always Blocks

Digital systems require memory elements like flip-flops. In Verilog, you create sequential logic (circuits with state) using an always block triggered by a clock edge. This is the primary method for describing registers, counters, and finite state machines.

You specify a clock edge using always @(posedge clk) for a rising-edge trigger. Within such a block, you use non-blocking assignments (<=) to model the simultaneous update of flip-flop outputs at the clock edge. This is a vital distinction: blocking assignments (=) evaluate and update immediately within the procedural flow, while non-blocking assignments (<=) schedule updates for the end of the timestep, correctly modeling parallel register updates.

// A simple 8-bit register with synchronous reset
always @(posedge clk) begin
    if (rst) begin
        q <= 8'b0;
    end else begin
        q <= d;
    end
end

This block synthesizes into an 8-bit flip-flop with a reset input. The reset condition is checked at the rising clock edge, making it a synchronous reset. For an asynchronous reset, you would include it in the sensitivity list: always @(posedge clk or posedge rst).

Creating Testbenches for Verification

A design is useless unless you can verify it works. A testbench is a special Verilog module that has no ports; its purpose is to instantiate your design (the Device Under Test, or DUT), apply stimulus to its inputs, and monitor its outputs. Since testbenches are for simulation only, you can use all Verilog constructs, including loops, delays, and file I/O.

The core of a testbench is an initial block, which executes once at the start of simulation, and always blocks to generate clock signals. You use system tasks like __MATH_INLINE_0__monitor to automatically track signal changes.

module testbench();
    reg clk, rst;
    reg [7:0] data_in;
    wire [7:0] data_out;

    // Instantiate the DUT
    my_module dut (.clk(clk), .rst(rst), .d(data_in), .q(data_out));

    // Generate a clock with 10-time-unit period
    always #5 clk = ~clk;

    // Apply stimulus
    initial begin
        clk = 0; rst = 1; data_in = 8'hFF;
        #20; // Wait 20 time units
        rst = 0;
        #100;
        $finish; // End simulation
    end
endmodule

This testbench generates a clock, applies a reset, and then de-asserts it. The # symbol denotes a delay, which is critical for creating realistic timing in simulation.

Simulation versus Synthesis: The Critical Mindset

The most important conceptual leap in learning Verilog is understanding the distinction between simulation behavior and synthesizable hardware descriptions. Verilog was originally a simulation language, so it contains many constructs (like # delays, initial blocks, and complex system tasks) that simulate behavior but cannot be mapped to physical hardware by a synthesis tool.

Your goal when writing code for synthesis is to describe a concrete hardware structure. Every line of code should answer the question: "What physical circuit does this represent?" For example, an always block without a complete if or case statement may simulate correctly but will synthesize into a latch, which is often a design error. A synthesizable subset of Verilog exists, and you must discipline yourself to use it. Tools will ignore or error on non-synthesizable constructs, reminding you that you are not writing software but defining a circuit's blueprint.

Common Pitfalls

1. Incomplete Branching in Always Blocks: Using an always @(*) block for combinational logic but failing to assign a value to the output in every possible branch of an if or case statement. This infers a latch, which is rarely intended for pure combinational circuits.

• Correction: Ensure every output is assigned a value in all branches. Use a default case or assign a default value at the start of the block.

1. Mixing Blocking and Non-Blocking Assignments Incorrectly: Using blocking assignments (=) within a clocked always block can cause simulation mismatches between pre- and post-synthesis results, as the order of assignments suddenly matters.

• Correction: Follow the golden rule: Use non-blocking assignments (<=) for all outputs of sequential logic (clocked blocks). Use blocking assignments (=) for intermediate variables within a combinational always @(*) block or for testbench code.

1. Treating Verilog Like a Software Language: Writing complex loops or algorithms without considering the massive parallel hardware they will generate. A for loop in synthesizable Verilog does not execute sequentially in time; it unrolls to create multiple copies of hardware.

• Correction: Always visualize the hardware. A loop with 4 iterations creates 4 instances of the logic inside it, all operating simultaneously.

1. Ignoring Simulation-Synthesis Mismatches: Relying solely on simulation results, especially those dependent on # delays, can hide critical race conditions or initialization problems that appear only in hardware.

• Correction: Always think in terms of clocks and registers. Use synchronous design practices (like resetting all flops) and rely on static timing analysis, not just simulation, to verify timing.

Summary

• Verilog modules are the primary hierarchical unit, communicating through input, output, and inout ports.
• Use continuous assignments (assign) for simple dataflow (combinational) logic and always blocks for procedural descriptions of both combinational (always @(*)) and sequential (always @(posedge clk)) circuits.
• The choice of assignment operator is critical: use blocking assignments (=) for combinational logic within an always block and non-blocking assignments (<=) for sequential logic to correctly model register updates.
• Testbenches are separate simulation-only modules that instantiate your design and apply stimulus using initial blocks, always blocks for clocks, and delay (#) statements.
• Maintain a strict synthesis-aware mindset; your code must describe physically realizable hardware, not just simulate correctly. The synthesizable subset of Verilog is a means to that end.