DL: Hazard Analysis in Combinational Circuits

In an ideal world, a digital logic circuit's output would change instantaneously and cleanly when its inputs change. In reality, brief, unwanted pulses called glitches can appear, potentially causing catastrophic errors in systems like counters or asynchronous controllers. Hazard analysis is the systematic process of identifying these temporary output errors and designing circuits to eliminate them, a critical skill for reliable digital system design.

Understanding the Core Problem: Static and Dynamic Hazards

A hazard is the potential for a circuit to produce a glitching output during a transition of its input variables. Hazards are categorized by their effect on the output. A static hazard occurs when an output should remain at a constant logic level (0 or 1) during an input change, but a brief opposite glitch appears. If the output is meant to stay at 1, it is a static-1 hazard; a glitch from 1 to 0 and back. If it should stay at 0, it is a static-0 hazard; a glitch from 0 to 1 and back.

In contrast, a dynamic hazard is more complex. It occurs when the output is supposed to change from 0 to 1 or 1 to 0, but instead oscillates multiple times (e.g., 0 -> 1 -> 0 -> 1) before settling at the correct final value. Dynamic hazards arise from multiple propagation paths with different delays within the circuit.

These glitches are caused by propagation delays in physical logic gates. Because different paths through a circuit have different numbers of gates and wire lengths, signals arrive at the final summing point at slightly different times. This temporary mismatch can cause the Boolean logic to flicker between true and false until all signals stabilize.

Identifying Hazards Using K-Maps

The Karnaugh Map (K-map) is your primary tool for predicting static hazards. A static hazard exists when two adjacent 1s (for a static-1 hazard) or two adjacent 0s (for a static-0 hazard) in the K-map are not covered by the same product (or sum) term in the circuit's simplified Boolean expression.

Consider the function $F=A\cdot C+\bar{B}\cdot C$. Its K-map reveals two adjacent 1s in the cells ABC = 101 and 111. These 1s are covered by the product term $A\cdot C$. Now, look at the adjacent 1s in cells ABC = 011 and 111. These are covered by the term $\bar{B}\cdot C$. However, the transition between the two pairs of adjacent 1s—specifically from cell 101 to 011—is not covered by a single product term. When inputs change from A=1, B=0, C=1 to A=0, B=1, C=1, the path is 101 -> 111 -> 011. The intermediate state 111 is still a 1, so no glitch is predicted? Wait, let's trace the logic: In the initial state (101), $A\cdot C=1$ and $\bar{B}\cdot C=0$, so F=1. In the final state (011), $A\cdot C=0$ and $\bar{B}\cdot C=1$, so F=1. During the transition, if B changes before A, we might momentarily hit state 111 where both terms are 1 (still F=1). But if A changes before B, we hit state 001, where both terms become 0, causing F to glitch to 0. This potential for a momentary 0 is the static-1 hazard. The K-map visually shows this because the adjacent 1s (101 and 011) are in different prime implicants and are not circled together.

Eliminating Static Hazards: Adding Consensus Terms

To eliminate a static hazard identified on a K-map, you add the missing product term that connects the two adjacent 1s that are in different groupings. This extra term is called a consensus term. For our example $F=A\cdot C+\bar{B}\cdot C$, the adjacent 1s at risk are 101 and 011. The consensus term is the product of the variables that remain constant during that transition. In moving from 101 to 011, variable A changes, B changes, but C remains 1. The consensus term is simply $C$.

The hazard-free expression becomes: $$F=A\cdot C+\bar{B}\cdot C+C$$ You can simplify this algebraically to $F=C$, but the purpose of the exercise is to see that the redundant term $C$ covers the gap between the other two implicants, ensuring that the output remains 1 throughout any single-variable transition between the covered cells. The added gate consumes more silicon area but guarantees glitch-free operation for that transition.

Analyzing Dynamic Hazards

Dynamic hazards are trickier and cannot be detected from a static K-map of the final output. They result from a circuit that has multiple, reconvergent paths with different delays from an input to the output. For an output to change three times (0->1->0->1), there must be at least three paths of differing delays.

To analyze a dynamic hazard, you must examine the circuit's transition diagram or perform a detailed timing analysis. This involves tracing all possible internal node states as an input changes. A dynamic hazard is often a symptom of poor design where a single input variable feeds into the circuit through multiple gates and then reconverges. The canonical example is a circuit that implements a function in a multi-level form after factoring, rather than a two-level SOP or POS form. The solution is often to redesign the circuit to a hazard-free two-level form, if possible, or to carefully manage and balance path delays.

Hazard-Free Design for Asynchronous Circuits

In asynchronous circuits (those without a global clock), hazards are not just an inconvenience—they can cause the circuit to transition to an incorrect, stable state. Therefore, hazard-free design is a strict requirement. The general procedure is:

1. Derive the Boolean function from the state transition requirements.
2. Map the function onto a K-map and identify all adjacent 1s (for static-1 hazards in SOP implementation) or adjacent 0s (for static-0 hazards in POS implementation).
3. Ensure all adjacent minterms (or maxterms) are covered by at least one common prime implicant (or implicate). This often means not using a minimally simplified expression*, but rather a more redundant, hazard-covering one.
4. Avoid multi-level realizations that create reconvergent fan-out, as these are breeding grounds for dynamic hazards. Stick to two-level AND-OR or OR-AND implementations based on your hazard-free cover.

*This is a key trade-off: minimal logic means fewer gates, but hazard-free design may require additional consensus terms, using more gates to ensure correctness.

Common Pitfalls

1. Assuming Simplified Logic is Always Best: The most algebraically simplified Boolean expression is often the most hazard-prone because it removes the redundant consensus terms that cover transitions. In critical applications, you must prioritize hazard elimination over gate minimization.
2. Ignoring Dynamic Hazards in Multi-Level Designs: A student might successfully eliminate all static hazards from a two-level SOP equation, then factor it to save gates. This factoring creates multiple paths and can introduce dynamic hazards. Always check multi-level designs with timing diagrams or transition analysis.
3. Misidentifying the Hazard Type on a K-Map: It's easy to confuse a static-1 with a static-0 hazard. Remember: if the starting and ending K-map cells are both 1, you are looking for a glitch to 0 (static-1 hazard). If they are both 0, you are looking for a glitch to 1 (static-0 hazard). The grouping rule is opposite for POS implementations.
4. Forgetting the Single-Input-Change Assumption: Standard hazard analysis assumes only one input changes at a time. In real systems, multiple inputs can change nearly simultaneously, creating more complex function hazards that cannot be fixed by logic design alone and require careful timing constraints or synchronous design techniques.

Summary

• Hazards are temporary glitches caused by unequal propagation delays in combinational logic, categorized as static (glitch on a steady output) or dynamic (oscillations during an output change).
• Karnaugh Maps are used to visually identify static hazards by finding adjacent minterms or maxterms not covered by a common implicant.
• Elimination of a static hazard is achieved by adding the consensus term—the product of variables unchanged during the risky transition—to the Boolean expression.
• Dynamic hazards arise from reconvergent fan-out with multiple path delays and require analysis via transition diagrams or circuit timing models.
• Asynchronous circuit design mandates hazard-free logic, which typically requires a non-minimal, two-level implementation where all adjacent cells in the K-map are covered to prevent glitches that could trigger erroneous state changes.