Switched-Capacitor Circuit Techniques

Switched-capacitor circuits are a cornerstone of modern analog integrated circuit design, enabling precise signal processing without the need for bulky resistors. By leveraging clock-controlled switches and capacitors, these circuits achieve accurate filtering and integration that are essential in communication systems, audio processing, and sensor interfaces. Mastering these techniques allows you to design compact, high-performance analog systems on chip where traditional resistor-based approaches fall short.

The Basic Principle: Emulating Resistors with Switches and Capacitors

At its core, a switched-capacitor circuit uses capacitors and clock-controlled switches—transistors operated by periodic digital signals—to simulate the behavior of a resistor. Imagine a simple scenario where a capacitor is alternately connected to two voltage nodes via switches. During one clock phase, the capacitor charges to the voltage at one node; during the next phase, it discharges to the other node, transferring a packet of charge. The average current flow over time depends on how much charge is moved per clock cycle, which is controlled by the capacitance value and the switching frequency. This charge-transfer mechanism effectively creates a resistive path, but without the physical resistor. For analog circuits in integrated circuits (ICs), this is revolutionary because resistors made from semiconductor materials are often large, imprecise, and temperature-sensitive, whereas capacitors and switches can be implemented efficiently and accurately.

Consider a basic switched-capacitor resistor emulation block: a capacitor $C$ connected between two switches that toggle at a clock frequency $f$. If the switches are controlled by non-overlapping clock phases, the capacitor continuously samples and transfers charge. The key insight is that the average current $I_{avg}$ flowing from one node to another is proportional to the voltage difference and the charge transferred per second. This leads to an equivalent resistance that dictates the circuit's time constants, just like a real resistor would.

Deriving the Equivalent Resistance

The resistance equivalence in a switched-capacitor circuit is derived from the charge transfer process. Suppose the capacitor $C$ is switched between two voltage sources, $V_1$ and $V_2$, at a clock frequency $f$ (where $f=1/T$ and $T$ is the clock period). In each cycle, the charge transferred when the capacitor connects from $V_1$ to $V_2$ is $Q=C(V_1-V_2)$. Since this happens every period $T$, the average current is $I_{avg}=Q/T=C(V_1-V_2)f$.

By Ohm's law, resistance $R=V/I$, so the equivalent resistance $R_{eq}$ seen between the two nodes is:

$$R_{eq}=\frac{V_1-V_2}{I_{avg}}=\frac{V_1-V_2}{C(V_1-V_2)f}=\frac{1}{fC}$$

Thus, $R_{eq}=1/(fC)$. This simple equation shows that the "resistance" is set by the capacitance $C$ and the clock frequency $f$, both of which can be precisely controlled in IC fabrication. For example, if $C=1\text{pF}$ and $f=1\text{MHz}$, then $R_{eq}=1/(10^6\times 10^{-12})=1\text{M}\Omega$. Emulating such a high resistance with a physical resistor would require significant chip area, but here it is achieved with a tiny capacitor and a clock signal.

Building Blocks: Switched-Capacitor Integrators

A fundamental building block in analog signal processing is the integrator, which outputs a voltage proportional to the integral of the input signal. In a traditional RC integrator, the time constant $\tau =RC$ depends on resistor and capacitor values, which are hard to control accurately in ICs. A switched-capacitor integrator replaces the resistor with a switched-capacitor network, leading to a time constant determined by capacitor ratios and clock frequency.

Consider a basic switched-capacitor integrator using an op-amp. The input resistor is replaced by a capacitor $C_1$ switched at frequency $f$, and a feedback capacitor $C_2$ integrates the charge. During each clock cycle, charge proportional to the input voltage is transferred onto $C_2$. The output voltage change per cycle is $\Delta V_{out}=-(C_1/C_2)V_{in}$, and over time, this approximates integration. The effective time constant $\tau$ of the integrator is:

$$\tau =\frac{1}{f}\cdot \frac{C_2}{C_1}$$

Here, $\tau$ depends on the ratio $C_2/C_1$ and the clock period $1/f$. Since capacitor ratios can be matched to within 0.1% or better in IC processes, and clock frequencies are derived from stable crystal oscillators, the time constant becomes extremely accurate and tunable. This precision is why switched-capacitor circuits are favored for filters and data converters.

From Integrators to Filters: Constructing Switched-Capacitor Filters

Switched-capacitor filters are constructed by cascading integrators and other switched-capacitor stages to achieve desired frequency responses, such as low-pass, high-pass, or band-pass characteristics. Because each integrator's time constant is set by capacitor ratios and clock frequency, the entire filter's cutoff frequencies and quality factors are precisely determined by these parameters, independent of absolute component values.

For instance, a second-order switched-capacitor filter (often called a biquad) can be built using two integrators in a feedback loop. The filter's transfer function—which defines how it attenuates or passes signals—has coefficients that are functions of capacitor ratios like $C_A/C_B$ and the clock frequency $f$. This means that by designing the capacitor layout carefully and setting the clock, you can implement filters with exact corner frequencies, such as 1 kHz or 10 MHz, without trimming or calibration. Moreover, since the clock frequency can be easily changed digitally, the filter characteristics can be programmed on the fly, enabling adaptive signal processing in applications like audio equalizers or communication channel selectors.

Advantages in Integrated Circuit Fabrication

The primary advantage of switched-capacitor techniques lies in their compatibility with modern IC fabrication. In ICs, resistors are typically implemented as doped semiconductor regions, which have poor tolerance (often ±20%), large temperature coefficients, and consume significant area for high values. Capacitors, on the other hand, can be made using thin oxide layers between metal or polysilicon plates, offering excellent matching (ratios accurate to 0.1%) and compact size. By combining these capacitors with MOS switches controlled by a clock, you achieve precise analog functions without resistors.

Additionally, the clock frequency $f$ is usually derived from a digital clock source, which is stable and easily integrated on-chip. This allows for accurate time constants that are proportional to $1/f$ and capacitor ratios, both of which are well-controlled in IC processes. As a result, switched-capacitor circuits enable complex analog systems—like analog-to-digital converters, phase-locked loops, and sensor interfaces—to be miniaturized onto single chips with performance that rivals discrete designs. For example, in a voice-band filter for a telephone system, switched-capacitor techniques ensure consistent cutoff frequencies across millions of devices without manual adjustment.

Common Pitfalls

When designing switched-capacitor circuits, several non-ideal effects can degrade performance if not properly managed.

1. Charge Injection and Clock Feedthrough: When MOS switches turn off, they inject charge from the gate channel into the capacitor nodes, causing voltage errors. Similarly, clock signals can capacitively couple into the signal path. To mitigate this, use differential circuits, bottom-plate sampling techniques, or dummy switches to cancel injected charge. For instance, in a sensitive integrator, charge injection can cause DC offsets; careful switch sizing and clock phasing are essential.

1. Non-Ideal Op-Amp Effects: The op-amps used in switched-capacitor integrators must have high gain and bandwidth to settle accurately within each clock phase. Finite op-amp gain can introduce gain errors in the integration, while slow settling leads to distortion. Design for sufficient gain-bandwidth product, and consider using auto-zeroing or correlated double sampling to reduce offset and noise.

1. kT/C Noise: Every time a capacitor is switched and charged, it introduces thermal noise with a power of $kT/C$, where $k$ is Boltzmann's constant and $T$ is temperature. This kT/C noise is fundamental and sets a lower limit on the signal-to-noise ratio. To minimize it, increase the capacitor size, but this trades off with speed and area. In high-resolution applications like audio ADCs, kT/C noise must be budgeted carefully in the design.

1. Parasitic Capacitances: In IC layouts, parasitic capacitances from wires and transistor junctions can couple to switched-capacitor nodes, affecting charge transfer and accuracy. Use symmetric layouts, shield sensitive lines, and model parasitics during simulation. For example, a parasitic capacitance to ground can alter the equivalent resistance, leading to filter frequency shifts.

Summary

• Switched-capacitor circuits use clock-controlled switches and capacitors to emulate resistors, enabling precise analog functions in ICs without large, imprecise physical resistors.
• The equivalent resistance is given by $R_{eq}=1/(fC)$, where $f$ is the clock frequency and $C$ is the capacitance, allowing time constants to be set by easily controlled parameters.
• Switched-capacitor integrators and filters achieve accurate frequency responses determined by capacitor ratios and clock frequency, both of which are well-matched and stable in integrated circuits.
• These techniques are ideal for IC fabrication due to area efficiency, excellent capacitor matching, and tunability via clock signals, supporting applications from filtering to data conversion.
• Key design challenges include managing charge injection, op-amp non-idealities, kT/C noise, and parasitic capacitances through careful circuit and layout techniques.