Analog Signal Multiplexing and Data Acquisition

In modern measurement and control systems, from industrial process monitoring to scientific instrumentation, engineers must digitize signals from dozens or even hundreds of sensors. Building a dedicated Analog-to-Digital Converter (ADC) for each channel is prohibitively expensive and complex. Analog signal multiplexing solves this problem by using a single, high-performance ADC to digitize many analog channels in sequence, forming the heart of a multiplexed data acquisition system (DAQ). This technique is a fundamental trade-off between cost, complexity, and the temporal fidelity of your measurements. Understanding the architectural choices and their limitations—particularly crosstalk, settling time, and sampling requirements—is crucial for designing systems that deliver accurate, trustworthy data.

The Core Principle: Sharing a Single ADC

At its simplest, a multiplexed DAQ system uses an analog multiplexer (MUX), which is an electronically controlled switch with multiple inputs and one output. A digital control signal selects which sensor channel is connected to the output at any given time. This output is then fed into a single, shared Analog-to-Digital Converter (ADC), which converts the analog voltage into a digital number a computer can process.

The primary advantage is dramatic cost and board space savings. A high-resolution, high-speed ADC is a significant system component. Using one ADC for 16 channels is far more economical than using 16 ADCs. The trade-off is that you do not measure all channels at exactly the same moment; you measure them one after another. The sequence and speed at which you cycle through the channels is controlled by the system's timing logic. For many applications, like slowly changing temperature or pressure readings, this sequential sampling is perfectly adequate. The critical task for an engineer is to determine when it is not adequate and what architectural changes are needed.

Key Specifications: Crosstalk and Settling Time

Two of the most critical non-ideal behaviors in a multiplexer directly impact measurement accuracy: channel-to-channel crosstalk and settling time.

Channel-to-channel crosstalk is the unwanted coupling of a signal from one channel into another. Imagine you are measuring a 10V signal on Channel 1 and a 10mV signal on Channel 2. Due to parasitic capacitance inside the multiplexer IC, a tiny fraction of the large signal can "leak" or couple onto the adjacent channel when you switch to it, corrupting the small measurement. This is often specified in the multiplexer datasheet as "Off Isolation" (e.g., -80 dB). High-precision systems measuring small signals adjacent to large ones require multiplexers with excellent off isolation. A practical mitigation strategy is to separate high-voltage and low-voltage signals into different multiplexer banks if possible.

Settling time is arguably the most overlooked yet vital specification. When the multiplexer switches from one channel to the next, the output does not instantly become a perfect replica of the new input voltage. The finite resistance of the switch (Ron) interacting with the capacitance of the output node (including the ADC's input capacitance) creates an RC circuit. The output must "settle" to within the desired accuracy of the new input voltage before the ADC can take a valid sample. This settling time depends on the voltage step size between channels and the system's RC time constant. A common design error is to initiate an ADC conversion immediately after commanding a channel switch, without allowing the full settling time to elapse, resulting in gross measurement errors. The system controller must insert a programmable delay between the switch command and the ADC "start conversion" signal.

Architectures for Simultaneous Sampling Requirements

What if your application requires knowledge of multiple signals at the same instant in time? For example, calculating power in a three-phase electrical system requires simultaneous voltage and current measurements, or structural vibration analysis requires correlated data from multiple accelerometers. Sequential sampling through a single multiplexer cannot achieve this.

The solution is to use sample-and-hold amplifiers (SHA) on each channel. In this architecture, each input channel has its own SHA circuit. A single "hold" command is issued to all SHAs simultaneously, capturing a snapshot of every channel's voltage at the same moment. Once the voltages are held constant, they can be slowly and sequentially multiplexed to the ADC for digitization without concern for the original signals changing. This enables quasi-simultaneous multi-channel measurement. The hold command defines the simultaneous sampling instant, while the subsequent digitization can take milliseconds. For the highest performance, some systems use a dedicated ADC for each channel, all triggered by a common sample clock, but this returns to a high-cost architecture. The per-channel SHA with a single multiplexed ADC is an excellent cost/performance compromise for many simultaneous sampling needs.

System Design Workflow and Considerations

Designing a robust multiplexed DAQ system follows a logical workflow. First, define your requirements: the number of channels, signal ranges, bandwidth, and required temporal relationship between channels (sequential vs. simultaneous). Next, select a multiplexer. Key parameters include the number of channels, on-resistance (Ron), off isolation, switching speed, and settling time to your required accuracy (e.g., to within 1 LSB of your ADC).

Then, select the ADC. Its resolution (e.g., 16-bit) and sampling rate must meet the needs of a single channel. Your total system sampling rate is the ADC's rate divided by the number of channels you cycle through. If you need to sample 10 channels at 1 kHz each, your ADC must support a minimum sample rate of 10 kilosamples per second (ksps). You must also ensure the ADC's input stage can be driven by the multiplexer output without degrading performance.

Finally, you design the timing sequence in firmware. This sequence must: 1) Select a MUX channel, 2) Wait for the full settling time, 3) Trigger the ADC conversion, 4) Read the ADC result, and then loop to the next channel. For systems with SHAs, the sequence becomes: 1) Issue a simultaneous "hold" to all SHAs, 2) Sequentially multiplex, settle, and digitize each held voltage.

Common Pitfalls

Ignoring Settling Time: As mentioned, this is the most frequent error. Always calculate the worst-case settling time based on the largest voltage swing between any two channels and the RC time constant formed by the MUX Ron and the total output capacitance. Verify with an oscilloscope if possible.

Overlooking Source Impedance: The sensor or signal-conditioning circuit driving each multiplexer input has an output impedance. This impedance combines with the MUX's Ron and the input capacitance of the SHA or ADC to create a different settling time constant for each channel if source impedances vary. Aim for low, matched output impedances on all driver circuits.

Misconfiguring Sample-and-Hold Amplifiers: When using per-channel SHAs, a crucial detail is the "acquisition time." After digitizing a held value, the SHA must be switched back to "sample" mode to track the live signal again. It needs sufficient acquisition time to settle to the live signal before the next simultaneous "hold" command is issued. If this time is too short, the held value will be inaccurate.

Forgetting About Multiplexer Drive Capability: Analog multiplexers are not ideal buffers. They have current drive limits. Connecting the MUX output directly to a high-capacitance ADC input or a long trace can create a heavy load, increasing settling time dramatically or causing oscillation. Often, a unity-gain buffer amplifier is placed between the MUX output and the ADC to provide a robust, low-impedance drive.

Summary

• Multiplexed data acquisition systems use analog switches to sequentially connect many sensor channels to a single, shared ADC, offering a cost-effective solution for multi-channel digitization.
• The non-ideal behavior of physical multiplexers introduces channel-to-channel crosstalk and a critical settling time delay after switching; both must be accounted for in component selection and system timing.
• When measurements from multiple channels must be temporally correlated, a simultaneous sampling architecture is required, typically implemented using sample-and-hold amplifiers (SHA) on each channel to capture signal snapshots at the same instant before sequential digitization.
• System design requires careful selection of the multiplexer and ADC based on channel count, signal range, and required throughput, followed by meticulous firmware timing that incorporates necessary settling and acquisition delays.
• Avoiding common pitfalls—like neglecting settling time, source impedance effects, and SHA acquisition time—is essential for achieving the full accuracy potential of a multiplexed DAQ system.