DL: Testability and Design for Test

Testing a modern digital chip with billions of transistors is not just difficult—it's impossible with traditional external probes alone. Design for Test (DFT) is the critical engineering discipline of incorporating testability features directly into a hardware design during its development, enabling efficient and effective detection of manufacturing defects before a product ships. Without DFT, you would have no economical way to guarantee that a chip, once fabricated, functions correctly, rendering advanced electronics unreliable and prohibitively expensive.

The Foundation: Fault Models and Testability

Before building test structures, you need a model for what can go wrong. The most fundamental and widely used model is the stuck-at fault model. It abstracts a physical defect (like a short to power or ground) as a logic signal being permanently "stuck-at-1" (SA1) or "stuck-at-0" (SA0) at a specific node in the circuit. While this doesn't cover all possible defects, it provides a robust, manageable target for test generation.

The primary goal is to detect these faults. You achieve this by applying a set of input patterns (test vectors) to the circuit and comparing the outputs to the expected, fault-free values. The effectiveness of a test set is measured by its fault coverage, calculated as the percentage of modeled stuck-at faults that the test set can detect. High fault coverage (often >95-99%) is a key requirement for production-grade designs. The challenge is that the internal states of a sequential circuit (with flip-flops) are not directly controllable or observable from the primary inputs and outputs, creating a major testability barrier.

Scan Chains: Making Internal State Accessible

The most common DFT technique to solve the controllability and observability problem is scan chain insertion. This involves modifying the design's flip-flops into scan flip-flops. Each scan flip-flop has a normal data input (D), a scan data input (SI), and a mode select signal (Scan Enable).

In normal operation (Scan Enable = 0), they function as standard flip-flops. In test mode (Scan Enable = 1), they are connected into one or long shift registers—the scan chains. This simple transformation revolutionizes testing:

1. Controllability: You can set any internal state by shifting in a desired pattern through the scan chain's input.
2. Observability: You can capture a system's response and shift out the contents of all flip-flops to observe the internal state.

The test process for a scan-based design follows a consistent rhythm:

• Shift Mode: A test pattern is shifted into all flip-flops via the scan chain.
• Capture Mode: The design returns to functional mode for one clock cycle, applying the scanned-in inputs to the combinational logic and capturing the results back into the flip-flops.
• Shift Mode: The captured response is shifted out (while the next test pattern is shifted in) and compared to the expected "golden" response.

This method reduces testing a complex sequential circuit to testing its combinational logic blocks, for which automated test pattern generation (ATPG) tools are highly effective.

Built-In Self-Test (BIST): On-Chip Test Automation

While scan chains provide access, they still require external testers to apply patterns and analyze responses. Built-In Self-Test (BIST) takes automation a step further by including pattern generation and response analysis circuitry on the chip itself. The most common architecture for logic BIST uses Linear Feedback Shift Registers (LFSRs).

An LFSR is a shift register whose input is a linear function of its previous state. It can generate a long, pseudo-random sequence of patterns to exercise the circuit under test. To analyze the output response, a Multiple Input Signature Register (MISR) is used. The MISR compresses the potentially massive output stream from thousands of test cycles into a short, fixed-length code called a signature. After the BIST sequence completes, the final signature is compared to a pre-computed "good" signature. If they match, the circuit passes the test.

BIST is particularly valuable for testing embedded memories (SRAM BIST) and for field testing, where external test equipment is unavailable. It trades off some fault coverage (pseudo-random patterns may not detect all faults) for tremendous savings in test time and equipment cost.

Boundary Scan (JTAG): Testing the Interconnections

Boundary scan, standardized as IEEE 1149.1 (often called JTAG after the Joint Test Action Group that created it), addresses a different problem: testing the physical interconnections between chips on a printed circuit board (PCB). As boards became denser with surface-mount components, physical probe testing became impossible.

Boundary scan adds a scan cell adjacent to every I/O pin on a chip. These cells are connected into a dedicated scan chain that rings the device—its boundary. In test mode, you can use this chain to:

• Drive signals onto the board's nets from one chip's output pins.
• Capture the logic levels on another chip's input pins.
• Thereby, verify opens, shorts, and proper soldering on the board without physical access.

Beyond board testing, the JTAG interface has become a ubiquitous standard for in-system programming of flash memory, debugging, and accessing on-chip debug modules.

Common Pitfalls

1. Neglecting Testability During RTL Design: Adding DFT as an afterthought is costly and inefficient. Considering testability during RTL coding—by avoiding gated clocks or asynchronous sets/resets that complicate scan insertion—saves significant time later.
2. Poor Scan Chain Partitioning and Ordering: Creating one extremely long scan chain maximizes shift time. Not balancing chain lengths or ordering cells physically leads to routing congestion and timing violations. The solution is to create multiple, balanced scan chains based on the physical layout.
3. Overlooking Power Dissipation During Test: A circuit switching at full speed during shift mode can draw significantly more current (switching power) than during normal operation, potentially causing voltage droop or damage. You must manage this by using scan chain gating, shifting at lower speeds, or using ATPG tools that generate low-power test patterns.
4. Confusing Fault Coverage with Defect Coverage: Achieving 99% stuck-at fault coverage does not guarantee 99% of manufactured chips are good. The stuck-at model does not cover all defect types (e.g., bridging, delay faults). The solution is to supplement stuck-at tests with other models (like transition fault tests) and use I_DDQ testing (measuring quiescent power supply current) to detect certain bridging defects.

Summary

• Design for Test (DFT) is an essential, integrated part of the digital design flow that makes manufacturing defect detection feasible and economical.
• The stuck-at fault model provides a practical abstraction for defects, and fault coverage is the key metric for evaluating a test's thoroughness.
• Scan chains are created by connecting scan flip-flops into shift registers, providing direct controllability and observability of internal states, transforming sequential circuit testing into combinational testing.
• Built-In Self-Test (BIST) uses on-chip Linear Feedback Shift Registers (LFSRs) for pattern generation and signature analysis for response compression, enabling at-speed and field testing.
• Boundary Scan (JTAG) standardizes access to I/O pins for testing board-level interconnections and is widely used for programming and debug.